Semiconductor chip, method of manufacturing the semiconductor chip and semiconductor chip package

ABSTRACT

In a semiconductor chip, a body has a top surface where a pattern is formed, an underside surface opposing the top surface and a plurality of side surfaces. A plurality of electrode pads are formed on the top surface of the body to connect to an external terminal. A shielding conductive film is formed on the surfaces excluding the top surface of the body where the pattern is formed. A conductive via is extended through the body to connect one of the electrode pads with the conductive film.

CLAIM OF PRIORITY

This application claims the benefit of Korean Patent Application No.2006-43946 filed on May 16, 2006 in the Korean Intellectual PropertyOffice, the disclosure of which is incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor chip package, moreparticularly, in which a shielding conductive film is connected to aground through a via hole, and a manufacturing method thereof.

2. Description of the Related Art

A high frequency module for use in a mobile telecommunication devicesuch as a mobile phone is constructed of a high frequency circuitincluding a high frequency semiconductor device and a periphery circuitthat are formed on a substrate thereof.

In general, current propagating in an electronic device induces electricfield and magnetic field therearound, thereby generating a space due toelectric potential difference. Here, the electric field changes withtime and generates electric magnetic field therearound. That is,regardless of the induction of the device, current flows to createelectromagnetic noise, which is an unnecessary energy.

Such electromagnetic noise, if transferred to other devices through apath, leads to degradation in performance and malfunction thereof.

To shield the electromagnetic noise and protect the semiconductordevice, a shielding technique for forming a shielding film has beenemployed.

FIGS. 1 a and 1 b illustrate a shielding structure according to theprior art.

FIG. 1 a is a cross-sectional view illustrating a high frequency modulehaving a high frequency semiconductor device 12 on a substrate 11shielded via a metal cap 12.

In the conventional shielding structure of the high frequency moduleshown in FIG. 1 a, the metal cap 13, if reduced in its thickness, cannotremain strong but is easily warped, potentially contacting the highfrequency device. To prevent short-circuit caused by contact between themetal cap 13 and the high frequency device, a certain space should bepreserved under the metal cap 13 to accommodate the metal cap 13 thatmay be warped. For example, the metal cap should be formed to athickness of 100 μm, and an inner space thereof should be designed to athickness of 80 μm. This physical volume stands in the way ofminiaturization of the high frequency module.

FIG. 1 b is a cross-sectional view illustrating the high frequencymodule in which the shielding film is formed via a metal film 15 afterresin molding.

In FIG. 1 b, the high frequency semiconductor device 12 is mounted onthe substrate 11 and resin molded to be hermetically sealed. Then theshielding film is formed on a surface of a mold 14 using the metal film15.

This leads to smaller physical volume compared to a case where the metalcap is adopted. Yet, the metal film formed on the mold is not connectedto a ground of the substrate, thus insignificant in terms of shieldingeffects.

SUMMARY OF THE INVENTION

The present invention has been made to solve the foregoing problems ofthe prior art and therefore an aspect of the present invention is toprovide a semiconductor chip which has a shielding layer formed thereonto connect to a ground, when the semiconductor chip is mounted on asubstrate, thereby to enhance shielding effects and ensure the chip tobe mounted in a minimal volume, and a semiconductor package having thesemiconductor chip.

Another aspect of the present invention is to provide a method ofmanufacturing the semiconductor chip having the shielding layer formedon a wafer.

According to an aspect of the invention, the invention provides asemiconductor chip including a body having a top surface where a patternis formed, an underside surface opposing the top surface and a pluralityof side surfaces; a plurality of electrode pads formed on the topsurface of the body to connect to an external terminal; a shieldingconductive film formed on the surfaces excluding the top surface of thebody where the pattern is formed; and a conductive via extending throughthe body to connect one of the electrode pads with the conductive film.

The electrode pad connected to the conductive via may be connected to anexternal ground and grounded.

The conductive film is formed only on the underside surface of the body.

According to another aspect of the invention, the invention provides asemiconductor chip package including the semiconductor chip as describedabove; a substrate where a ground lead pattern and a plurality of leadpatterns are formed; and a plurality of bumps disposed between therespective electrode pads of the semiconductor chip and the respectivelead patterns of the substrate to electrically connect the semiconductorchip with the substrate.

The electrode pad connected to the via hole is connected to the groundlead pattern of the substrate.

The conductive film is formed only on the underside surface of thesemiconductor chip.

According to further another aspect of the invention, the inventionprovides a method for manufacturing a semiconductor chip including:

forming via holes in a wafer including unit chip areas to connect froman electrode pad on a top surface of a wafer where a pattern is formedto an underside surface of the wafer opposing the top surface so that atleast one of the via holes is formed in each of the unit chip areas;

filling the via hole with conductive material;

forming a conductive film on the underside surface of the wafer tocontact the conductive material filled in the via hole; and

cutting the wafer into unit chips.

The manufacturing method may further include forming a shieldingconductive material on a side surface of the cut semiconductor chip.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features and other advantages of thepresent invention will be more clearly understood from the followingdetailed description taken in conjunction with the accompanyingdrawings, in which:

FIGS. 1 a and 1 b are cross-sectional views illustrating a shieldingstructure according to the prior art;

FIG. 2 is a cross-sectional view illustrating a semiconductor chippackage according to an embodiment of the invention;

FIG. 3 a is a perspective view illustrating a semiconductor chipaccording to another embodiment of the invention, and FIG. 3 b is across-sectional view illustrating a semiconductor chip package; and

FIG. 4 a to 4 d are perspective views illustrating a flow of a methodfor manufacturing a semiconductor chip of FIG. 3 a.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Exemplary embodiments of the present invention will now be described indetail with reference to the accompanying drawings.

FIG. 2 is a cross-sectional view illustrating a semiconductor chippackage having a semiconductor chip mounted on a substrate according toan embodiment of the invention.

Referring to FIG. 2, the semiconductor chip 20 is flip-bonded onto thesubstrate 21.

The semiconductor chip 20 has a body 22 provided with a plurality ofelectrode pads 28 on a top surface 22 a thereof.

A conductive film 25 is formed on an underside surface 22 b and sidesurfaces of the body 22 of the semiconductor chip where the electrodepads are not formed. Also, a via hole 27 is perforated through the topsurface 22 a and one of the side surfaces of the body 22.

The package substrate 21 is manufacturable by the same process as theone for fabricating a printed circuit board (PCB), or by HighTemperature Chemical Cleaning (HTCC) or Low Temperature Co-firedCeramics (LTCC).

A circuit pattern is disposed on the package substrate 21 to input andoutput a signal, and vias are formed to be connected respectively withelectrode pads on the circuit pattern to form a ground lead pattern. Theground lead pattern is configured to electrically connect the electrodepads on overlying and underlying layers together.

As shown in FIG. 2, bumps 23 made of metal are formed on the leadpatterns of the circuit pattern disposed on the package substrate 21,and the semiconductor chip is mounted on the electrode pads 28 via thebumps 23. The flip-bonded semiconductor chip allows the electrode pads28 to be electrically connected to the lead patterns on the packagesubstrate 21 by the bumps 23.

In the semiconductor chip, the electrode pads 28 on the top surface 22 aof the body 22 are connected to the substrate 21 by the bumps 23, someof which are ground bumps 23 a connected to a ground of the substrate.The bumps 23 formed between the lead patterns 29 of the substrate 21 andthe electrode pads 28 of the semiconductor chip are made of gold,copper, aluminum or alloys thereof and serve to connect wires of thesubstrate with the semiconductor chip.

The ground bumps 23 a are in direct contact with a conductive via filledwith a conductive material in the via hole 27 and serve to electricallyconnect the conductive film 25 with the ground. Of course, although theconductive via 27 a is directly connected to the bumps 23, theconductive via 27 a, if electrically connected to the ground bumps 23 aon the substrate, may realize this feature of the invention.

In this fashion, the conductive film 25 formed on the underside surface22 b and the side surfaces of the body 22 of the semiconductor chip iselectrically connected to the ground. As a result, electromagnetic wavegenerated from the semiconductor chip is induced to flow toward theground, and thus blocked. This accordingly inhibits occurrence ofnoises. Further, this shields electromagnetic wave induced to thesemiconductor chip from outside, thereby suppressing interference fromthe electromagnetic wave.

To easily form the conductive film 25 on the underside surface 22 b andthe side surfaces of the semiconductor chip, conductive paint isdirectly applied on the top surface and side surfaces of thesemiconductor chip or sprayed thereonto.

FIG. 3 a is a perspective view illustrating a semiconductor chipaccording to an embodiment of the invention.

Referring to FIG. 3 a, the semiconductor chip has a body provided withelectrode pads 38 on a top surface 32 a thereof where patterns areformed, and a metal film 35 on an underside surface 32 b thereof. Themetal film 35 has a via hole 37 perforated through the body 32 of thesemiconductor chip. The metal film 35 is brought in contact with aconductive via 37 a filled with a conductive material in the via hole37. The via hole 37 is connected to the electrode pads 38 on the topsurface 32 a of the semiconductor chip body 32.

The via hole 37 can be formed by laser processing or dry etching such asreactive ion etch. The via hole 37 may feature various shapes such as acircle, a triangle and a polygon. The via hole 37 may have a uniformcross-section. Alternatively, the via hole 37 may have a cross-sectionthat is greater or smaller in proportion to its proximity to the topsurface 32 a thereof.

The via hole 37 is filled with a conductive material to form theconductive via 37 a and extended to the electrode pads on the topsurface 32 a of the semiconductor chip body 32 to electrically connectthe conductive film 35 with a ground on the substrate.

The conductive via 37 a can be formed by electroplating and theconductive material adopts all electroplatable metals such as gold (Au),silver (Ag), copper (Cu), aluminum (Al), nickel (Ni), and tungsten (W).

Alternatively, the conductive via 37 a may be formed by vacuumevaporation, sputtering, chemical vapor deposition and by filling-up andsintering of a conductive paste. The conductive material for filling thevia hole 37 is exemplified by gold (Au), silver (Ag), copper (Cu),aluminum (Al), nickel (Ni), tungsten (W) and alloys thereof.

To easily form the conductive film 35 on the underside surface 32 b ofthe semiconductor chip body 32, conductive paint is directly applied tothe underside surface of the semiconductor chip body or sprayedthereonto.

FIG. 3 b is a cross-sectional view illustrating a semiconductor chippackage having a semiconductor chip mounted on a substrate.

Referring to FIG. 3 b, the semiconductor chip is flip-bonded onto thesubstrate 31.

The semiconductor chip has a body 32 provided with a plurality ofelectrode pads 38 on a top surface 32 a thereof.

A conductive film 35 is formed on an underside surface 32 b of thesemiconductor chip body 32 where electrode pads are not formed. Also, avia hole 37 is perforated through the top surface 32 a and the undersidesurface 32 b of the semiconductor chip body 32.

Further, the electrode pads 38 on the top surface 32 a of thesemiconductor chip body 32 are connected to lead patterns 39 on thesubstrate 31 via bumps 33, some of which are ground bumps 33 a connectedto a ground on the substrate. The bumps formed between the lead patterns39 of the substrate 31 and the electrode pads 38 of the semiconductorchip are made of gold, copper, aluminum or alloys thereof, and serve toconnect wires of the substrate with the chip.

The ground bumps 33 a are made in direct contact with the conductive via37 a filled with a conductive material in the via hole 37 and serve toelectrically connect the conductive film 35 to the ground on thesubstrate. Of course, although the conductive via 37 a is directlyconnected to another one of the bumps 33, the conductive via 37 a, ifelectrically connected to the ground bumps 33 a on the substrate, mayrealize this feature of the invention.

Although not illustrated, a barrier metal film may be formed tofacilitate bonding between the ground bumps 33 a and the conductive via37 a and prevent cracks from heat accompanied by use of the chip,thereby ensuring reliability of the chip. The barrier metal film may bemade of one selected from a group consisting of titanium (Ti), titaniumnitride (TiN), tantalum nitride (TaN), Ti/TiN and Ta/TaN. The barriermetal film is preferably formed by chemical vapor deposition.

The via hole 37 is filled with a conductive material to form theconductive via 37 a and extended to the ground bumps 33 a formed on theelectrode pads disposed on the top surface 32 a of the semiconductorchip body 32 to electrically connect the conductive film 35 with theground on the substrate.

In this fashion, the conductive film 35 formed on the underside surface32 b of the semiconductor chip body 32 is electrically connected to theground. As a result, electromagnetic wave generated from thesemiconductor chip is induced to flow toward the ground, and thusblocked. This accordingly inhibits occurrence of noises. Also, thisshields electromagnetic wave induced to the semiconductor chip from theoutside, thereby suppressing interference from the electromagnetic wave.

The conductive film 35 can be formed merely on the underside surface 32b of the semiconductor chip body 32 when individual semiconductor chipsare applied with a conductive film material separately from one another.

Here, at least one via hole is perforated through the top surface andunderside surface of the semiconductor chip body 32 and filled with aconductive material. Then a conductive film is formed on the undersidesurface of the semiconductor chip body to be brought in contact with theconductive material. The conductive film 35 can be easily formed bydirectly applying or spraying conductive paint for shieldingelectromagnetic wave.

Alternatively, in a structure where the conductive film is formed on theunderside surface of the semiconductor chip, the via hole and theconductive film are formed on a wafer before being cut into the unitchips, and then cut into the unit chips. This accordingly simplifies amanufacturing method.

FIGS. 4 a to 4 d illustrate a manufacturing method in which thesemiconductor chip of FIG. 3 a is fabricated on a wafer.

To fabricate the semiconductor chip having a conductive film therein onthe wafer, the wafer is prepared, at least one via hole is formed ineach of unit chip areas on the wafer, a conductive material is filled inthe via hole, a conductive film is formed on an underside surface of thewafer and the wafer is cut into unit chips.

Referring to FIG. 4 a, a via hole is formed on each of the unit chipareas to connect from electrode pads on the top surface of the waferwhere patterns and the electrode pads are formed to the undersidesurface of the wafer. FIG. 4 a is a perspective view in which theunderside surface of the wafer faces upward. The via hole 47 is formedby mechanical polishing or laser processing. To realize an aspect of theinvention, at least one via hole is necessarily formed on each of theunit chip areas. Here, the via hole is connected to one of the electrodepads disposed around patterns (not illustrated) formed on the topsurface of the wafer. That is, the electrode pads are connected to aground of the substrate.

Referring to FIG. 4 b, the via hole 47 formed on each of the unit chipareas is filled with a conductive material to form a conductive via 47a. This allows the conductive film 45 on the underside surface of thesemiconductor chip body 42 to electrically connect to the ground of thesubstrate.

Referring to FIG. 4 c, the conductive film is formed on the undersidesurface of the wafer. The conductive film 45 can be formed by directlyapplying or spraying conductive paint for shielding electromagneticwave. This simplifies a process and saves material costs compared with acase where the conductive film is formed-on each of the unit chips.

Here, the conductive film 45 is in direct contact with the conductivevia 47 a filled with a conductive material in the via hole 47.Preferably, the conductive film 45 is made of the same conductivematerial filled in the via hole 47.

Referring to FIG. 4 d, the wafer is cut into each of the unit chips toproduce the semiconductor chip according to the invention. Theconductive film 45 is formed on the underside surface of thesemiconductor chip body 42 and brought in contact with the conductivematerial filled in the via hole 47. Accordingly, the conductive via 47 aconnects the conductive film 45 with the ground of the substrate.

Furthermore, optionally a shielding conductive material may be formed onside surfaces of the cut semiconductor chip to boost shielding effectsof the conductive film.

Although not illustrated, the cut semiconductor chip is flip bonded ontothe substrate to connect the conductive via to the ground of thesubstrate, thereby producing the semiconductor chip package according tothe invention.

The embodiments and the accompanying drawings are illustrative only butdo not limit the invention. Thus, the conductive film and the via holecan be located variously.

As set forth above, according to exemplary embodiments of the invention,when a semiconductor chip is mounted on a substrate, a shielding metalfilm is connected to a ground to boost shielding effects ofelectromagnetic wave and ensure the chip to be mounted in a minimalvolume.

In addition, the semiconductor chip can be fabricated on a wafer tosimplify a manufacturing process.

While the present invention has been shown and described in connectionwith the preferred embodiments, it will be apparent to those skilled inthe art that modifications and variations can be made without departingfrom the spirit and scope of the invention as defined by the appendedclaims.

1. A semiconductor chip comprising: a body having a top surface where apattern is formed, an underside surface opposing the top surface and aplurality of side surfaces; a plurality of electrode pads formed on thetop surface of the body to connect to an external terminal; a shieldingconductive film formed on the surfaces excluding the top surface of thebody where the pattern is formed; and a conductive via extending throughthe body to connect one of the electrode pads with the conductive film.2. A semiconductor chip according to claim 1, wherein the electrode padconnected to the conductive via is grounded.
 3. A semiconductor chipaccording to claim 1, wherein the conductive film is formed only on theunderside surface of the body.
 4. A semiconductor chip packagecomprising: a semiconductor chip including: a body having a top surfacewhere a pattern is formed, an underside surface opposing the top surfaceand a plurality of side surfaces; a plurality of electrode pads formedon the top surface of the body to connect to an external terminal; ashielding conductive film formed on the surfaces excluding the topsurface of the body where the pattern is formed; and a conductive viaextending through the body to connect one of the electrode pads with theconductive film, a substrate where a ground lead pattern and a pluralityof lead patterns are formed; and a plurality of bumps disposed betweenthe respective electrode pads of the semiconductor chip and therespective lead patterns of the substrate to electrically connect thesemiconductor chip with the substrate.
 5. The semiconductor chip packageaccording to claim 4, wherein the electrode pad connected to the viahole is connected to the ground lead pattern of the substrate.
 6. Thesemiconductor chip package according to claim 4, wherein the conductivefilm is formed only on the underside surface of the semiconductor chip.7. A method for manufacturing a semiconductor chip comprising: formingvia holes in a wafer including unit chip areas to connect from anelectrode pad on a top surface of a wafer where a pattern is formed toan underside surface of the wafer opposing the top surface so that atleast one of the via holes is formed in each of the unit chip areas;filling the via hole with conductive material; forming a conductive filmon the underside surface of the wafer to contact the conductive materialfilled in the via hole; and cutting the wafer into unit chips.
 8. Themethod according to claim 7, further comprising: forming a shieldingconductive material on a side surface of the cut semiconductor chip.